With decrease in size of large scale integrated circuits (LSIs), processing techniques for controlling leakage current interference between transistor elements are increasingly gaining technical difficulties. LSI element isolation is achieved by a method of forming gaps such as grooves or holes in a silicon (Si) substrate between elements to be isolated, and depositing insulating material in the gaps. The insulating material may often be an oxide film such as a silicon oxide film. The silicon oxide film is formed by oxidation of the Si substrate, CVD (Chemical Vapor Deposition), or SOD (Spin On Dielectric).
With recent miniaturization, to fill micro structures, particularly, a gap structure, which is deep in a vertical direction or narrow in a horizontal direction, with oxide, a filling method using a CVD method has reached a technology limit. In response to this background, a filling method using oxide having fluidity, i.e., SOD, tends to be increasingly employed. For SOD, a coating insulating material containing an inorganic or organic component called SOG (Spin On Glass) is being used. Although this material has been employed for LSI manufacturing processes before appearance of CVD oxide films, since processing technology has non-fine feature size in a range from 0.35 μm to 1 μm or so, a modification method after coating was allowed by performing heat treatment of 400 degrees C. in a nitrogen atmosphere.
On the other hand, there is an increasing need to reduce a thermal load of transistors. The reason for reducing the thermal load includes prevention of excessive diffusion of impurities, such as boron, arsenic, phosphorus, and so on, which are injected for operation of transistors, prevention of aggregation of metal silicide for electrodes, prevention of performance variation of work function metal material for gates, secure of writing/reading repetition lifetime of memory devices, etc.
However, since the minimum feature size of a semiconductor device represented by recent LSI, DRAM (Dynamic Random Access Memory), or flash memories is smaller than 50 μm width, it is difficult to achieve miniaturization and improvement of manufacturing throughput while maintaining quality, and make a process temperature low.